SEDL / STP / STP1382-EB / STP13489S

Single-Wafer Gate Dielectric Technologies for Sub-0.18 μm Applications

Miner, G
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Xing, G
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Yokota, Y
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Jaggi, A
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Sanchez, E
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Chen, C
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Lopes, D
Thermal Processing Organization, Applied Materials, Santa Clara, CA

Pages: 10    Published: Jan 2000

Download this paper for $25 PDF (224K)          View License Agreement
Abstract

The continued aggressive scaling of device dimensions presents serious challenges in transistor design and process integration. In particular for the gate dielectric, the reduction in equivalent oxide thickness challenges the limits of current process and equipment technologies. Single-wafer oxidation technologies are fundamentally different from their batch furnace counterparts and can address these challenges. The differences in single-wafer reaction chemistry are responsible for significant improvements in gate dielectric integrity. Rapid thermal processing also makes possible high levels of nitrogen incorporation, while maintaining this reliability improvement. These improvements will be increasingly important for the next several device generations.