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Single-Wafer Gate Dielectric Technologies for Sub-0.18 m Applications Pages: 10 Published: Jan 2000
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View License Agreement Source: STP1382-EB Abstract The continued aggressive scaling of device dimensions presents serious challenges in transistor design and process integration. In particular for the gate dielectric, the reduction in equivalent oxide thickness challenges the limits of current process and equipment technologies. Single-wafer oxidation technologies are fundamentally different from their batch furnace counterparts and can address these challenges. The differences in single-wafer reaction chemistry are responsible for significant improvements in gate dielectric integrity. Rapid thermal processing also makes possible high levels of nitrogen incorporation, while maintaining this reliability improvement. These improvements will be increasingly important for the next several device generations.
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