Chip seal research advocates for performing rational design computations prior to construction to determine the initial chip and binder application rates. Research indicated that a major concern in chip seal construction industry is the lack of following a formal/documented computational design approach. This study is a result of research that investigated ways to improve chip seal design specifications in Oregon State, focusing on field application rates. The objective of this article is to encourage agencies and contractors to adopt a formal established design approach to determine their aggregates and binder application rates. This is established through identifying the parameters considered in the design while showing straightforward procedures to follow formal design approaches. Chip seal design calls for conducting laboratory and field evaluations and uses the results as input data to estimate the appropriate quantities of materials. Thus, involved parties at the design stage are required to (1) understand the properties of chip seal materials (aggregate and binder), (2) identify the pre-seal road condition, and (3) use said information in the design process. This study uses various roadways located in Klamath Falls, Oregon to verify the importance of using rational design procedures. The roadways were constructed in accordance with Oregon Department of Transportation specifications; however, application rates were based upon the agency’s previous experience rather than using a rational design approach. The study compares roadways’ infield application rates and rationally estimated rates based upon two commonly used methodologies, namely McLeod and New Zealand. Findings shows that roadways constructed using infield application rates close to the rationally estimated rates had better embedment and a longer predicted life span when compared to the rest of roadways that had excessive aggregate amounts and less binder content.
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