| ||Format||Pages||Price|| |
|8||$55.20||  ADD TO CART|
This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current density and temperature stress.
This guide is being withdrawn because the committee is not aware of the need to maintain the standard. Reference to the standard will remain available, but at this time, the committee does not wish to actively maintain the standard.
Formerly under the jursidiction of Committee F01 on Electronics and the direct responsibility of Subcommittee F01.11 on Nuclear and Space Radiation Effects, this test method was withdrawn in December 2009 with no replacement.
1.1 This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current density and temperature stress. This test method is intended to be used only when the failure distribution can be described by a log-Normal distribution.
1.2 This test method is intended for use as a referee method between laboratories and for comparing metallization alloys and metallizations prepared in different ways. It is not intended for qualifying vendors or for determining the use-life of a metallization.
1.3 The test method is an accelerated stress test of four-terminal structures (see Guide F 1259M) where the failure criterion is either an open circuit in the test line or a prescribed percent increase in the resistance of the test structure.
1.4 This test method allows the test structures of a test chip to be stressed while still part of the wafer (or a portion thereof) or while bonded to a package and electrically accessible by means of package terminals.
1.5 This test method is not designed to characterize the metallization for failure modes involving short circuits between adjacent metallization lines or between two levels of metallization.
1.6 This test method is not intended for the case where the stress test is terminated before all parts have failed.
1.7 This test method is primarily designed to analyze complete data. An option is provided for analyzing censored data (that is, when the stress test is halted before all parts under test have failed).
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
2. Referenced Documents (purchase separately) The documents listed below are referenced within the subject standard but are not provided as part of the standard.
F1259M Guide for Design of Flat, Straight-Line Test Structures for Detecting Metallization Open-Circuit or Resistance-Increase Failure Due to Electromigration (Metric)
F1261M Test Method for Determining the Average Electrical Width of a Straight, Thin-Film Metal Line (Metric)
Other StandardsEIA/JEDEC Standard37— Lognormal Analysis of Uncensored Data, and of Singly Right-Censored Data Utilizing the Persson and Rootzen Method
|Link to Active (This link will always route to the current Active version of the standard.)|
ASTM F1260M-96(2003), Standard Test Method for Estimating Electromigration Median Time-to-Failure and Sigma of Integrated Circuit Metallizations [Metric] (Withdrawn 2009), ASTM International, West Conshohocken, PA, 1996, www.astm.orgBack to Top