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Electronics Committee Is Making Sparks

ASTM Committee F01 on Electronics announces several standards activities this month.

Membrane Switches

ASTM Membrane Switch Subcommittee F01.18 has created a series of electrical, mechanical, environmental, cosmetic and aesthetic tests that world-wide manufacturers can use to prove their switches meet customer needs.

Low-cost test methods are a boon to membrane-switch manufacturers and purchasers, and Subcommittee F01.18 has developed 25 standard test methods that cover switch life, tail creasing, dielectric withstand and thermal shock, standard terminology for membrane switches, and more.

According to committee member Dennis Webster, both membrane manufacturers, and original equipment manufacturers who purchase custom membrane switches for their product, must know what specifications their switch will meet. “As an OEM, these are the methods that should be on your drawings and those against which you insist upon receiving verification documentation,” says Webster, an engineering manager who has worked with membranes for 20 years. “As a manufacturer, these are the methods you should incorporate within your facility, validating that you are a quality vendor.”

The subcommittee also welcomes participation on a task group that is drafting standard test procedures for electroluminescent lamps. To learn more about ASTM’s membrane switch standards or participate on the task group, contact co-chairmen Alan Burk, ALMAX, Kirkland, Wash. (phone: 425/ 889-9417) or Neil Bolding.

Compound Semiconductors

Committee F01 requests feedback from semiconductor stakeholders on three new activities from Subcommittee F01.15 on Compound Semiconductors.

Backside Processing — A subcommittee task group is gathering industry comments on Work Item WK1050, Compound Semiconductor Backside Processing, which is standard as guidance for backside processing of compound semiconductors. To review the draft standard, contact Scott Orthey, manager, ASTM Technical Committees (phone: 610/832-9730).

Subcommittee chairman Austin Blew highly encourages members of the compound semiconductor industry to reply with comments. “I’m hoping to get more of the people that have to use this information on a day-to-day basis,” he says, “telling us what to include or not to include.”

Task group chairman Maria Huffman, a Manufacturing Development engineer with Agilent Technologies, Inc., Santa Rosa, Calif., says the task group hopes to establish basics of the backside process that can be accepted as an industry baseline. “For silicon there is an International Roadmap (ITRS),” says Huffman, in silicon 16 years prior to working with III-V semiconductors. In the silicon industry, she says, abundant information exists for building various devices or overcoming specific technical challenges for people entering the business or seeking guidance. “That type of information is not readily available for compound semiconductors,” she says. As a first project, the task group is producing standard guidance for performing backside processing of III-V materials. “This is a good suite of processes to address since there is a lot of excellent, public information available to condense into a useful guide,” she says.

Huffman agrees with Blew on the importance of obtaining comments from a cross-section of the semiconductor industry for the draft standard. “We need more help from different metrology and processing-equipment vendors,” she says. “If we do not have adequate instrumentation, let’s say, for measuring a parameter (or parameters) at certain times during a specific process, standards development is a very nice way to start getting vendors involved who can be thinking about the problem, either improving current equipment or creating next generation equipment.”

Stakeholders have expressed significant interest in developing standard guidance for backside processing and metrology but, Huffman says, some are reluctant because of intellectual property rights. “We do not have to disclose any intellectual property,” she says. Instead, the task group intends to offer generic, useful information on the processing of III-V semiconductors, she concludes. Direct technical questions to Huffman (phone: 707/577-4895).

Backside Processing Metrology — Subcommittee F01.15 is developing Work Item WK 881, Backside Processing Metrology for Compound Semiconductors. The proposed standard, which is being balloted at ASTM, will cover metrology for TTV, TIR, sori and restrained flatness measurements. A task group that drafted WK 881 welcomes input from users and producers of sapphire substrates and sapphire wafer carriers and instrument manufacturers.

“The goal of this task group is to evaluate the applicability of the existing ASTM measurement standards that were written for the silicon industry, and are now being used for the compound semiconductor industry,” says task group chairman Tom Parsons, process engineer, INSACO, Inc., Quakertown, Pa. “A new standard will be proposed to describe test methods that are more applicable to compound semiconductor processing (e.g., sapphire wafer carriers and sapphire substrates).”

Parsons specializes in improving and developing processes for high-precision grinding, lapping and/or polishing of ultra-hard materials (non-metals) such as ceramics, sapphire, quartz, and silicon nitride. Explaining the benefit of the proposed standard, he says: “The silicon measurement methods for bow and warp explain how to measure silicon using capacitive displacement probes which works for silicon material, but not for sapphire. Sapphire is not conductive, so typically an optical/interferometry technique is used. The silicon methods typically establish the median plane as the plane of reference (perhaps due to the measurement technique) whereas the users of sapphire substrates and wafer carriers are more interested in the form of the surface with respect to the front or back best-fitting plane (not the median plane).”

For further information, contact Tom Parsons, INSACO, Inc., Quakertown, Pa. (phone: 215/536-3500, ext. 48).

PHEMT Mobility Round Robin — ASTM Subcommittee F01.15 on Compound Semiconductors is organizing a PHEMT Mobility Round Robin to determine the repeatability and reproducibility of mobility and sheet-charge density of two different structures of PHEMT (pseudomorphic high electron mobility transistor) wafers.

Laboratories who wish to participate will need the Destructive Hall System based on ASTM F 76, Standard Test Method Measuring Resistivity and Hall Coefficient and Determining Hall Mobility in Single Crystal Semiconductors Method A - Van der Pauw or a non-destructive RF system. Task group leader, Danh Nguyen, electrical engineer, Lehighton Electronics Inc., Lehighton, Pa. (phone: 610/377-5990) will provide samples (10 x 10 mm and 40 x 40 mm) in carriers cleaved from wafers supplied by MBE Technologies PTE Limited of Singapore. These wafers replaced those originally supplied by IQE of Bethlehem, Pa., which were damaged by the sawing vendor.

“We hope to use the information learned from it to improve ASTM F 76, and SEMI Draft Document 3436 [of Semiconductor Equipment and Materials International],” says Nguyen. “We should be able to compare the results of the Destructive DC and Non-Destructive RF measurements with thin caps (approx. 20-50A) and production caps (approx. 400-500A) results on two different structures,” he adds. “Hopefully this will lead to availability of mobility and sheet charge density reference material and to the standardization of software to separate the cap and 2DEG Channel mobility and sheet charge density.”

For further technical details, contact subcommittee chairman Austin Blew, Lehighton Electronics Inc., Lehighton, Pa. (phone: 610/377-5990).

Committee F01 meets Jan. 12-15 in Tampa, Fla. //

Copyright 2003, ASTM