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A computer program has been developed which extends the existing technique for calculating global circuit yield factor of lateral geometric design rules by process simulation. The current paper describes the inclusion of resistor limits as part of the general yield model. The program depends upon a reliable data base including: 1) geometric tolerances, 2) skews or offsets of critical dimensions during processing, 3) tolerable minimum separation of circuit element edges, 4) film tolerances of resistivity and thickness, and 5) resistor design limits.
The program incorporates conventional means of original design rule creation.
process simulation, yield analysis, modeling, design rules
process engineer, Sierra Semiconductor, San Jose, Ca