SYMPOSIA PAPER Published: 01 January 2000
STP13489S

Single-Wafer Gate Dielectric Technologies for Sub-0.18 μm Applications

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The continued aggressive scaling of device dimensions presents serious challenges in transistor design and process integration. In particular for the gate dielectric, the reduction in equivalent oxide thickness challenges the limits of current process and equipment technologies. Single-wafer oxidation technologies are fundamentally different from their batch furnace counterparts and can address these challenges. The differences in single-wafer reaction chemistry are responsible for significant improvements in gate dielectric integrity. Rapid thermal processing also makes possible high levels of nitrogen incorporation, while maintaining this reliability improvement. These improvements will be increasingly important for the next several device generations.

Author Information

Miner, G
Thermal Processing Organization, Applied Materials, Santa Clara, CA
Xing, G
Thermal Processing Organization, Applied Materials, Santa Clara, CA
Yokota, Y
Thermal Processing Organization, Applied Materials, Santa Clara, CA
Jaggi, A
Thermal Processing Organization, Applied Materials, Santa Clara, CA
Sanchez, E
Thermal Processing Organization, Applied Materials, Santa Clara, CA
Chen, C
Thermal Processing Organization, Applied Materials, Santa Clara, CA
Lopes, D
Thermal Processing Organization, Applied Materials, Santa Clara, CA
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Details
Developed by Committee: F01
Pages: 122–131
DOI: 10.1520/STP13489S
ISBN-EB: 978-0-8031-5431-5
ISBN-13: 978-0-8031-2615-2