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This test method covers the measurement of MOSFET (see Note 1) linear threshold voltage under very low sweep rate or d-c conditions. It is a d-c conductance method applicable in the linear region of MOSFET operation where a drain voltage V
Note 1-MOS is an acronym for metal-oxide semiconductor, FET is an acronym for field-effect transistor.
Formerly under the jurisdiction of Committee F01 on Electronics, this test method was withdrawn in June 2006 in accordance with section 10.6.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.
1.1 This test method covers the measurement of MOSFET (see Note 1) linear threshold voltage under very low sweep rate or d-c conditions. It is a d-c conductance method applicable in the linear region of MOSFET operation where a drain voltage V D of approximately 0.1 V is typical.
Note 1--MOS is an acronym for metal-oxide semiconductor; FET is an acronym for field-effect transistor.
1.2 This test method is applicable to both enhancement-mode and depletion-mode MOSFETs, and for both silicon-on-insulator (SOI) and bulk-silicon MOSFETs. The test method specifies positive voltage and current conventions specifically applicable to n-channel MOSFETs. The substitution of negative voltage and negative current make the test method directly applicable to p-channel MOSFETs.
1.3 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this test method.
1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.