STP1323: Measurement of Stress Distributions on Silicon IC Chips Using Piezoresistive Sensors

    Suhling, Jeffrey C.
    Professor, Auburn University, Auburn, AL

    Jaeger, Richard C.
    Distinguished University Professor, Auburn University, Auburn, AL

    Pages: 26    Published: Jan 2001


    Structural reliability of integrated circuit chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, and operating temperatures. A powerful method for experimental evaluation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezoresistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented.


    stress sensor, piezoresistive, test chip, electronic packaging

    Paper ID: STP42145S

    Committee/Subcommittee: E08.04

    DOI: 10.1520/STP42145S

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