Published: Jan 2001
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Structural reliability of integrated circuit chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, and operating temperatures. A powerful method for experimental evaluation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezoresistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented.
stress sensor, piezoresistive, test chip, electronic packaging
Suhling, Jeffrey C.
Professor, Auburn University, Auburn, AL
Jaeger, Richard C.
Distinguished University Professor, Auburn University, Auburn, AL
Paper ID: STP42145S