STP1323

    Measurement of Stress Distributions on Silicon IC Chips Using Piezoresistive Sensors

    Published: Jan 2001


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    Abstract

    Structural reliability of integrated circuit chips in electronic packages continues to be a major concern due to ever-increasing die size, circuit densities, power dissipation, and operating temperatures. A powerful method for experimental evaluation of silicon die stress distributions is the use of test chips incorporating integral piezoresistive sensors. In this paper, a review is made of the state-of-the-art in the area of silicon piezoresistive stress sensor test chips. Developments in sensor theory, calibration methods, and packaging applications are presented.

    Keywords:

    stress sensor, piezoresistive, test chip, electronic packaging


    Author Information:

    Suhling, Jeffrey C.
    Professor, Auburn University, Auburn, AL

    Jaeger, Richard C.
    Distinguished University Professor, Auburn University, Auburn, AL


    Paper ID: STP42145S

    Committee/Subcommittee: E08.04

    DOI: 10.1520/STP42145S


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