SEDL / STP / STP804-EB / STP36170S

Process Technology Requirements for VLSIC Fabrication

Kumar, R
Burroughs Corporation, San Diego, Calif.

Nowak, MM
Burroughs Corporation, San Diego, Calif.

Tyler, EH
Burroughs Corporation, San Diego, Calif.

Vinson, MA
Burroughs Corporation, San Diego, Calif.

Pages: 9    Published: Jan 1983

Download this paper for $25 PDF (140K)          View License Agreement
Abstract

The fabrication of high-density, high-performance integrated circuits to provide a lower cost per function requires N-channel metal-oxide-semiconductor (NMOS) circuits with smaller minimum dimensions, thinner gate oxides, and shallower junction depths. This paper provides an overview of process technology constraints and requirements for the fabrication of scaled NMOS very-large-scale integrated circuits (VLSICs). Devices with shallow junction depths are required to minimize short channel effects in such VLSICs; this places numerous constraints on processing. These constraints require low-temperature processing and cause several deviations from present production processing techniques. We shall review some solutions to these constraints, especially in the junction formation and low pressure chemical vapor deposition areas.