The Effect of Wafer Flatness on Yield by Off Line Computer Simulation of the Photolithographic Process

SEDL / STP / STP850-EB / STP32649S

The Effect of Wafer Flatness on Yield by Off-Line Computer Simulation of the Photolithographic Process

Denes, L
Product Manager, Metrology Products, GCA Corporation, Tropel Division, Fairport, New York

Pages: 17 Published: Jan 1984

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Abstract

This paper describes a powerful new computer program which has the ability to directly simulate virtually all popular projection and stepper type aligners. The effects on yield of such metrologies as global wafer retilting, exposure by exposure retilting and autofocusing will be analyzed. Three point and the new seven point mirror projection aligner image plate geometries will also be characterized.

The results of several process simulations will be presented using the new program's powerful graphic displays which yield a view of wafer shape never seen before.

Keywords:
wafer flatness characterization, microphotolithography, phase-modulated grazing-incidence interferometer, computer simulation, yield enhancement, relative focal plane, depth of focus

Paper ID: STP32649S
Committee/Subcommittee: F01.15
DOI: 10.1520/STP32649S

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