STP990

    VLSI Defect Detection, Classification, and Reduction from In-Process and Post-Process Sram Inspections

    Published: Jan 1989


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    Abstract

    As device dimensions shrink to the order of one micron and chip sizes approach 100mm2, containing more than 105 transistors, some of the standard yield enhancement practices lose effectiveness. In particular, in-process inspections suffer as it becomes increasingly probable that defects will not be detected due to the reduced circuit dimensions and increased pattern complexity. Another area hard hit is post process probe yield failure analysis. With the greater number of components and functions per chip extremely large vector sets (thousands) must be run to adequately characterize and isolate failures at probe test. This results in long test times as well as a significant increase in the time required for data analysis to isolate circuit failures. Adoption of a static RAM (SRAM) as a yield vehicle can reinstate the effectiveness of both of these techniques for VLSI. The repetitiveness and regularity of the RAM pattern facilitates visual inspection, even at the micron level, and bit mapping provides easy test isolation of defects at post process probing. The application of a SRAM in a VLSI yield enhancement strategy for defect classification and reduction is discussed in this paper.

    Keywords:

    VLSI, yield, random defects, gross defects, SRAM


    Author Information:

    Parks, HG
    electronics engineerchemical engineertest technicianmembers of IC Process Engineering Branch, VLSI Technology Laboratory at the General Electric Company Corporate Research and Development Center, Schenectady, NY

    Logan, CE
    electronics engineerchemical engineertest technicianmembers of IC Process Engineering Branch, VLSI Technology Laboratory at the General Electric Company Corporate Research and Development Center, Schenectady, NY

    Fahrenz, CA
    electronics engineerchemical engineertest technicianmembers of IC Process Engineering Branch, VLSI Technology Laboratory at the General Electric Company Corporate Research and Development Center, Schenectady, NY


    Paper ID: STP26045S

    Committee/Subcommittee: F01.06

    DOI: 10.1520/STP26045S


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