STP960: Palladium Silicide Contact Process Development for VLSI

    Singh, RN
    staff research scientist, General Electric Company, Corporate Research and Development, Schenectady, New York

    Pages: 13    Published: Jan 1987


    Abstract

    A process for forming self-aligned small-area palladium silicide ohmic contacts to shallow junction silicon is described. A number of processing steps such as thin-film deposition, thermal annealing for silicide formation, and etching of unreacted palladium are developed in conjunction with modern materials characterization techniques such as SEM, SIMS and RBS. The results indicate that palladium films of ≤500A thickness have good adherence to silicon and silicon dioxide. The metal-rich, dense, and continuous Pd2Si readily forms on reaction of silicon with palladium upon thermal annealing. The siliciding reaction disrupts the native oxide and forms an intimate silicide-silicon interface. Unreacted palladium is etched in an aqueous etching solution, but extreme care is necessary to avoid palladium oxide formation during annealing, which leads to etching difficulties. Based on these results an optimum palladium silicide contact process for VLSI is proposed. Excellent contact resistance values between 11 and 25Ω are obtained for palladium silicide contacts of 1.25µm diameter using the optimum process.

    Keywords:

    palladium silicide-silicon contacts, VSLI contacts, VSLI processing


    Paper ID: STP25759S

    Committee/Subcommittee: F01.06

    DOI: 10.1520/STP25759S


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