STP960

    Effects of Gettering on Epi Quality for CMOS Technology

    Published: Jan 1987


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    Abstract

    The quality of silicon epitaxial layer deposited on n+ substrates has been improved by applying a pre-epitaxial intrinsic gettering process to the substrates. The epilayer defect density was decreased, while the junction breakdown voltage and the product yield of 16K CMOS Static RAM were both increased. The bulk microdefects generated by the IG process were observed and believed to be the key to the quality improvement of epitaxial layer. The better quality of epitaxial layer deposited on heavily phosphorus doped substrates, compared to those deposited on heavily antimony doped substrates, was attributed to the microdefects formed close to the epi/substrate interface. Although the epi/substrate transition width of n/n+(P) is wider than that of n/n+(Sb), no significant difference in current gain of parasitic bipolar transistors has been observed.

    Keywords:

    silicon epitaxy, intrinsic gettering, latch-up, junction breakdown voltage


    Author Information:

    Daniel Wong, C-C
    senior process development engineersenior staff engineeranalytical lab manager, Integrated Device Technology, Inc.Applied Materials, Inc.Siltec Corp., Santa ClaraSanta ClaraMountain View, CACACA

    Borland, JO
    senior process development engineersenior staff engineeranalytical lab manager, Integrated Device Technology, Inc.Applied Materials, Inc.Siltec Corp., Santa ClaraSanta ClaraMountain View, CACACA

    Hahn, S
    senior process development engineersenior staff engineeranalytical lab manager, Integrated Device Technology, Inc.Applied Materials, Inc.Siltec Corp., Santa ClaraSanta ClaraMountain View, CACACA


    Paper ID: STP25740S

    Committee/Subcommittee: F01.06

    DOI: 10.1520/STP25740S


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