Volume 42, Issue 6 (November 2013)

    Design and Evaluation of Efficient Router Architecture for Triplet-Based Network-on-Chip Topology

    (Received 27 July 2013; accepted 2 January 2014)

    Published Online: 2014

    CODEN: JTEOAD

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    Abstract

    A network-on-chip (NoC) router serves an important function in network communication performance. A high-performance router will help build a high-throughput, power-efficient, and low-latency NoC. However, the existing baseline router of a triplet-based NoC topology cannot fully optimize the potential performance, because it does not consider the characteristics of triplet-based NoC topology. This paper presents the topology-related router architecture for a triplet-based topology, called X Router. The baseline router architecture is optimized using four measures, namely, simplified crossbar switch, express virtual channel, group-priority scheme, and shared buffer organization. Simulation results using the cycle-accurate simulator Noxim show that the X Router cannot only decrease traffic latency and energy consumption, but also improve throughput over the baseline router architecture.


    Author Information:

    Zhang, Yang
    School of Information Science and Engineering, Hebei University of Science and Technology, Hebei,


    Stock #: JTE20130182

    ISSN: 0090-3973

    DOI: 10.1520/JTE20130182

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    Author
    Title Design and Evaluation of Efficient Router Architecture for Triplet-Based Network-on-Chip Topology
    Symposium , 0000-00-00
    Committee B01