Volume 25, Issue 1 (January 1997)

    Testing and Design of CMOS D-Latches

    (Received 27 June 1994; accepted 29 July 1996)


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    The CMOS D-latch is an important block in the design of sequential circuits. Thus, a new fully testable CMOS D-latch (FTD) is proposed. A comprehensive test set that includes possible physical failures is developed. This test set is then applied to the FTD. The cost of implementation, analysis, and simulation of the FTD are all presented. Application of the FTD-latch to build a polarity-hold shift register is shown.

    Author Information:

    Aissi, C
    Howard University, Washington, DC,

    Olaniyan, J
    Howard University, Washington, DC,

    Stock #: JTE11325J

    ISSN: 0090-3973

    DOI: 10.1520/JTE11325J

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    Title Testing and Design of CMOS D-Latches
    Symposium , 0000-00-00
    Committee F01