ISSN: 1945-7553
CODEN: JTEVAB
Page Count: 9

Testing and Design of CMOS D-Latches

Aissi, C
Howard University, Washington, DC,

Olaniyan, J
Howard University, Washington, DC,

(Received 27 June 1994; accepted 29 July 1996)

Abstract

The CMOS D-latch is an important block in the design of sequential circuits. Thus, a new fully testable CMOS D-latch (FTD) is proposed. A comprehensive test set that includes possible physical failures is developed. This test set is then applied to the FTD. The cost of implementation, analysis, and simulation of the FTD are all presented. Application of the FTD-latch to build a polarity-hold shift register is shown.

Keywords:
CMOS D-latch, digital circuits, fully testable D-latch (FTD), transistor

Paper ID: JTE11325J
DOI: 10.1520/JTE11325J
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